Access Type

Open Access Thesis

Date of Award


Degree Type


Degree Name



Electrical and Computer Engineering

First Advisor

Pepe Siy


The Viterbi decoding algorithm is used to decode convolutional codes and is found in many systems that receive digital data that might contain errors. The use of error-correcting codes has proven tobe an effective way to overcome data corruption in digital communication channels. In previous works, researchers describe the Viterbi Algorithm, but the accuracy does not exceed 10% of data points. Also, a lot of previous works do not follow IEEE 802.16 new specifications. Viterbi decoders are generally implemented using programmable digital signal processors (DSPs) or special purpose chip sets and application-specific integrated circuits (ASICs). Here, we aim to implement such decoder on an FPGA. In This paper, we provide a more accurate Viterbi decoder according to IEEE 802.16 specifications. We used VHDL hardware description language to implement the algorithm. We also used OrCAD Capture V9.1 to compile, synthesize, and simulate our code. IEEE 802.16 standard specifies the air interface of fixed point-to-multipoint broadband wireless access (BWA) systems providing multiple services. This standard is intended to enable rapid worldwide deployment of broadband wireless access products. The new IEEE 802.16 specifications require a Viterbi block decoder with constraint length of 3, traceback length of 32, and minimum throughput requirement of 44.8 Mbps. The Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx XC4005XL FPGA.